1. Field of the Invention
The present invention relates to a memory test method, and more particularly to a build-in self-test method of a memory module for enhancing reliability of a system including the memory module without reducing the system effectiveness.
2. Description of Related Art
Today, chips are designed and manufactured for deep sub-micron (DSM) technology, and more memories are embedded such that memory yield has a serious effect on the yield of the entire chip. Accordingly, in order to improve the yield of chips, a repairable memory is needed.
In addition, as the degree of integration of a semiconductor device increases and the functions become more complicated, a variety of methods for efficiently testing such semiconductor devices are being developed. To guarantee the yield of products, before the products having memories are sent out of a factor, a build-in self-test method (BIST) is utilized for eliminating failure from the products. Nevertheless, good products may be damaged after being packaged, transported, and welded on print circuit board (PCB). Accordingly, the memories included in the products will be tested again on system product line with the BIST method to guarantee performance. While users get the products such as computers, BIOS (basic input output system) also tests memories in the computers with the BIST method when the users turn on the computers. Obviously, memories reliability is an important issue as known from above.
The traditional method for improving the memories reliability is simply utilized under the above conditions. As the use of electronic products prevails, such as a server continuously working for several years, or a baked mobile phone which is left in car, systems in these electronic products are easy to be down if no active method is utilized to guarantee the memories quality.
Recently, error correction code technology (ECC) is mostly used for guaranteeing memories reliability of a system in a server. However, the use of ECC technology in the system will cause efficiency loss about 5%. This is an undesirable condition for a high efficient product.